library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity nBitRightShift is
generic (n : integer := 8);
port(A,B : in std_logic_vector(n-1 downto 0);
Y : out std_logic_vector(n-1 downto 0)
);
end nBitRightShift;

architecture struct of nBitRightShift is
--create array of vectors to hold each of n shifters
type shifty_array is array (n-1 downto 0) of std_logic_vector (n-1 downto 0);
signal Y_array : shifty_array;
begin
generate_shifters : for i in 0 to n-1 generate
--generate a register for each possible shift
--Shift A and move it into the register
Y_array (i)(n-i-1 downto 0) <= A(n-1 downto i);
fill : if i>0 generate
--fill the rest of the register with '0's
Y_array(i)(n-1 downto n-i) <= (others => '0');
end generate fill;
end generate generate_shifters;
--The output will be tied to the register that contains the requested shift
Y <= Y_array(to_integer(unsigned(B)));
end struct;